Processing systems typically utilize a virtual-addressing scheme such that virtual addresses in corresponding virtual address spaces are mapped to physical addresses of memory locations and input/output (IO) interfaces through the use of page tables and a translation lookaside buffer (TLB). The advent of processor virtualization has complicated this virtual-to-physical address mapping due to the number of different virtual address spaces that may be implemented within a processing system and due to the desire to provide effective isolation among implemented virtual machines. A processing system may support TLB tagging using an identifier representing a corresponding virtual address space. These identifiers often have tens of bits and the TLB hit logic required to handle searches of this size generally are prohibitively complex to implement. Conventional virtualized processing systems therefore often utilize software-based address mapping at the cost of the considerable overhead required to maintain and implement these address mappings under software control.